Conventionally, in order to form a wiring circuit on a semiconductor substrate, a layer of Al or Al alloy is deposited on a surface of a substrate by a sputtering process or the like, and then unnecessary portions are removed from the layer by a chemical dry etching process using a photoresist or the like for a mask pattern. However, as the level of integration of circuits increases, the width of wiring becomes narrower to thus increase current density, resulting in generating thermal stress in the wiring and increasing temperature of the wiring. As a result, the layer of Al or Al alloy becomes thinner due to stress migration or electromigration, and finally to cause a breaking of the wiring.
Hence, copper has been drawn much attention as a wiring material because of its lower resistance and higher reliability. However, it is difficult to form wiring by etching after a layer is deposited on a surface of a substrate and then performing a patterning process, which is different from a conventional method using Al. Therefore, there has been attempted a damascene process in which a wiring groove is preformed in a substrate and filled with copper by chemical vapor deposition (CVD), sputtering, plating, or the like, and then unnecessary portions are removed from the surface of the substrate by chemical mechanical polishing (CMP), for thereby forming wiring in the groove.
Among these processes for filling a wiring groove with copper, the plating process has drawn much attention because of the following advantages. The processing cost is lower than that in other processes, and pure copper material can be obtained, and the process can be performed at such a low temperature that a substrate is not damaged. The plating process mainly comprises an electroless plating process, which is mainly performed by a chemical process, and an electrolytic plating process, which is performed by an electrochemical process. The electrolytic plating process is generally more efficient than the electroless plating process.
Since copper is liable to be oxidized and corroded and diffused into SiO2, wiring is generally formed after a wiring portion on a base material of the substrate is covered with a barrier layer of metal nitride such as TiN, TaN, and WN. Since the sheet resistance of this barrier layer is prohibitively larger than the resistance of the plating liquid, it has been difficult to perform uniform electrolytic plating on the barrier layer formed over the surface of the substrate.
Conventionally, a seed layer of copper is formed on the barrier layer by a sputtering process or a CVD process, and then plated with copper by an electrolytic plating process to fill fine recesses formed in the substrate with copper. However, it is difficult to uniformly deposit a layer on a wall of the fine recess by the sputtering process, and the CVD process introduces impurities into the deposited layer. Further, when the design rule is further decreased from about 0.18 μm to 0.10 μm, there is no dimensional margin to form a seed layer having a thickness of 0.02 to 0.05 μm within the recess.
On the other hand, in the electroless plating process, since the plating layer is grown in isogonic directions from a side wall or a bottom surface of the fine recess, an inlet of the recess is covered with metal grown from the side wall and hence, a void tends to be formed in the recess. In addition, since the plating rate of the electroless plating process is about one-tenth as slow as that of the electrolytic plating process, the electroplating process is inefficient.